Browsing by Author "Erdem S.S."

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    Efficient ID-based authentication and key agreement protocols for the session initiation protocol
    (Turkiye Klinikleri, 2015) Kilinč H.H.; Allaberdiyev Y.; Yanik T.; Erdem S.S.
    In a widely deployed VoIP system tens of thousands of clients compete for the SIP proxy server's authentication service. SIP protocol implementations have to meet certain QoS and security requirements. In this study new ID-based protocols are proposed for the SIP authentication and key agreement protocols. These protocols minimize the use of expensive pairing functions but still resist notable attacks. The security of the proposed protocols are analyzed and demonstrated with security proofs based on the BJM security model. Finally, the performance overhead of the proposed protocols are compared to ID-based SIP authentication and key agreement protocols given in the literature. © TUBITAK.
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    A General Digit-Serial Architecture for Montgomery Modular Multiplication
    (Institute of Electrical and Electronics Engineers Inc., 2017) Erdem S.S.; Yanik T.; Çelebi A.
    The Montgomery algorithm is a fast modular multiplication method frequently used in cryptographic applications. This paper investigates the digit-serial implementations of the Montgomery algorithm for large integers. A detailed analysis is given and a tight upper bound is presented for the intermediate results obtained during the digit-serial computation. Based on this analysis, an efficient digit-serial Montgomery modular multiplier architecture using carry save adders is proposed and its complexity is presented. In this architecture, pipelined carry select adders are used to perform two final tasks: adding carry save vectors representing the modular product and subtracting the modulus from this addition, if further reduction is needed. The proposed architecture can be designed for any digit size δ and modulus θ. This paper also presents logic formulas for the bits of the precomputation -θ-1 mod 2δ used in the Montgomery algorithm for δ ≤ 8. Finally, evaluation of the proposed architecture on Virtex 7 FPGAs is presented. © 2017 IEEE.