A General Digit-Serial Architecture for Montgomery Modular Multiplication

dc.contributor.authorErdem S.S.
dc.contributor.authorYanik T.
dc.contributor.authorÇelebi A.
dc.date.accessioned2024-07-22T08:10:52Z
dc.date.available2024-07-22T08:10:52Z
dc.date.issued2017
dc.description.abstractThe Montgomery algorithm is a fast modular multiplication method frequently used in cryptographic applications. This paper investigates the digit-serial implementations of the Montgomery algorithm for large integers. A detailed analysis is given and a tight upper bound is presented for the intermediate results obtained during the digit-serial computation. Based on this analysis, an efficient digit-serial Montgomery modular multiplier architecture using carry save adders is proposed and its complexity is presented. In this architecture, pipelined carry select adders are used to perform two final tasks: adding carry save vectors representing the modular product and subtracting the modulus from this addition, if further reduction is needed. The proposed architecture can be designed for any digit size δ and modulus θ. This paper also presents logic formulas for the bits of the precomputation -θ-1 mod 2δ used in the Montgomery algorithm for δ ≤ 8. Finally, evaluation of the proposed architecture on Virtex 7 FPGAs is presented. © 2017 IEEE.
dc.identifier.DOI-ID10.1109/TVLSI.2017.2652979
dc.identifier.issn10638210
dc.identifier.urihttp://akademikarsiv.cbu.edu.tr:4000/handle/123456789/15417
dc.language.isoEnglish
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.subjectElectrical engineering
dc.subjectHardware
dc.subjectCryptographic applications
dc.subjectDigit-serial architecture
dc.subjectIntermediate results
dc.subjectModular Multiplication
dc.subjectMontgomery algorithm
dc.subjectMontgomery modular multiplication
dc.subjectMontgomery modular multiplier
dc.subjectnocv1
dc.subjectProposed architectures
dc.subjectAdders
dc.titleA General Digit-Serial Architecture for Montgomery Modular Multiplication
dc.typeArticle

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